Jane Street has released an open challenge: reverse engineer a custom ASIC from its final mask layout. The firm has published every metal, routing, and active transistor layer of the chip, along with sample inputs and outputs. Participants must recover a netlist from the physical layout, figure out what the circuit actually does, and then extract a specific string value as their answer.
Jane Street released a puzzle for reverse engineering an ASIC.
— gaby lorenzi (@gabyllorenzi) August 10, 2026
i've been looking for a project to go deeper in chip design, and i think this is going to be the one. everything's open source, let's see how far i get!! pic.twitter.com/hayNOin2MQ
Submissions close September 4th, 2026.
What the Puzzle Demands
This is not a beginner exercise. The challenge is structured in three stages: extract the netlist, understand the circuit's purpose, and simulate it to produce the correct output. Jane Street has published the GDS file on GitHub, and participants can open it using free tools like KLayout or Magic VLSI. The puzzle uses an open-source process design kit, meaning no proprietary tooling is required.
To help newcomers get started, the firm included a warm-up design consisting of two shift registers, an adder, and a comparator. It outputs success when A + B equals 496. The warm-up comes with Verilog source, a gate-level netlist, and the final GDS, giving solvers a reference for the extraction flow.
The Recruiting Angle
Jane Street's hardware team designs FPGAs and ASICs that, in the firm's own words, "run some of the fastest trading systems in the world." The daily work, according to the blog post, involves "staring at a sea of gates, timing reports, or waveforms and slowly teasing out what's really going on."
That description is a near-perfect summary of what the puzzle asks participants to do. This is not accidental. The challenge doubles as a filter for the exact kind of engineer Jane Street wants on its hardware team.
The firm has long treated puzzles as a proxy for the type of problem-solving it values. Its monthly puzzle archive draws thousands of solvers, and hardware-focused challenges like the 2025 Advent of FPGA event have built a reputation in the RTL design community. The ASIC puzzle extends that tradition to the physical design layer, where talent is scarcer and the learning curve is steeper.
A Pipeline for Custom Silicon
There is a practical dimension to this as well. Jane Street has teased a follow-up competition later this year in which participants will design their own chips. The most interesting entries will be fabricated.
That is not a throwaway promise. Fabricating custom chips, even on a tiny scale, is expensive. If Jane Street is willing to tape out community-designed silicon, it is betting that open challenges can surface ideas and people it would not find through conventional recruiting. The reverse-engineering puzzle primes participants for that next step. Understanding a layout backwards is good preparation for building one forwards.
Why This Matters
The hardware talent pipeline is thin. University programs produce far more software engineers than digital designers, and the niche discipline of physical design and verification is smaller still. For a firm whose trading infrastructure depends on custom silicon and ultra-low-latency FPGAs, finding people who can reason at the transistor level is a strategic imperative.
The ASIC puzzle is a public audition. Anyone who solves it demonstrates that they can do the actual work. That is a signal a resume cannot provide.
Jane Street says it is hiring for FPGA and ASIC internships and full-time roles. The puzzle page links directly to those listings.
